An abnormal clock detector is disclose, f or example, in Japanese Patent Application Laid-open No. 4-306930. In this abnormal clock detector, as shown in FIG. 16, two different clocks (CK.sub.1 and CK.sub.2) are compared with each other to detect which one of them is abnormal.
In the conventional abnormal clock detector shown in FIG. 16, since an abnormal clock is detected, the clocks CK.sub.1 and CK.sub.2 having different duty ratio or frequency are input a frequency divider 100 and a frequency divider 101, respectively. Frequency of the input clocks CK.sub.1 and CK.sub.2 are respectively divided by frequency division ratios M.sub.1 and M.sub.2 in the frequency divider 100 and the frequency divider 101. The clock CK.sub.1 whose frequency was divided in the frequency divider 100 is output from the frequency divider 100 as a clock CK.sub.4 having frequency f.sub.4. The clock CK.sub.2 whose frequency was divided in the frequency divider 101 is output from the frequency divider 101 as a clock CK.sub.3 having frequency f.sub.3. The clock CK.sub.3 is input into a timing generator 102. Here, the frequency division ratios M.sub.1 and M.sub.2 are arbitrary natural numbers satisfying a relation of 2.multidot.f.sub.4.gtoreq.f.sub.3.
The clock CK.sub.4 output from the frequency divider 100 are input into counters 103 and 104, respectively, as input data. The clock CK.sub.3 input into the timing generator 102 is output from the timing generator 102 as a reset pulse CK.sub.5, and the output reset pulse CK.sub.5 is further input into the counters 103 and 104, respectively, as reset pulses.
The counter 103 counts, during pulse interval of the reset pulse CK.sub.5, leading edges of the pulse of the clock CK.sub.4 which is input data, and the counted pulse number S.sub.up is output. The counter 104 counts, during pulse interval of the reset pulse CK.sub.5, leading edges of the pulse of the clock CK.sub.4 which is input data, and the counted pulse number S.sub.down is output.
The pulse numbers S.sub.up and S.sub.down respectively output from the counters 103 and 104 are input into an adder 105. In the adder 105, the pulse number S.sub.up is added to the pulse number S.sub.down, and the number of state change during pulse interval of the clock CK.sub.4 of the reset pulse CK.sub.5, i.e., an addition value N.sub.1 which is the number of pulse rising and falling edges of the pulse is output.
The addition value N.sub.1 from output the adder 105 is input into a comparator 106 as input data B and to a comparator 107 as input data A. A reference value N.sub.2 is further input into the comparator 107 as input data B, and the input data A is compared with the input data B to judge whether a relation A&lt;B is satisfied. That is, the comparator 107 judges whether a relation of N.sub.1 &lt;N.sub.2 is satisfied, and if the relation of N.sub.1 &lt;N.sub.2 is satisfied, an error signal E.sub.2 is output from the comparator 107.
Here, the reference value N.sub.2 is an arbitrary natural number satisfying a relation of N.sub.2.multidot.f.sub.3 &lt;2.multidot.f.sub.4.ltoreq.(N.sub.2 +1).multidot.f.sub.3. N.sub.2 +1 is input into the comparator 106 as input data A, and like the comparator 107, the input data A is compared with the data B to judge whether a relation of A&lt;B is satisfied. That is, the comparator 106 judges whether a relation of N.sub.1 &gt;N.sub.2 +1 is satisfied. If the relation N.sub.1 &gt;N.sub.2 +1 is satisfied, an error signal E.sub.1 is output from the comparator 106.
Since the pulse interval of the reset pulse CK.sub.5 is determined by the frequency f.sub.3 of the clock CK.sub.3, a relation of N.sub.1.ltoreq.N.sub.2 +1 is established with respect to the reference value N.sub.2 satisfying the relation N.sub.2.multidot.f.sub.3.ltoreq.2.multidot.f.sub.4 &lt;(N.sub.2 +1).multidot.f.sub.3 in the clock CK.sub.4 (frequency f.sub.4) and the reset pulse CK.sub.5 (frequency f.sub.3) respectively input into the counters 103 and 104. Therefore, when a relation N.sub.1 &gt;N.sub.2 +1 is satisfied in the comparator 106, this means that the frequency f.sub.4 of the CK.sub.4 is higher than its original frequency or the frequency f.sub.3 of the CK.sub.3 is lower than its original frequency, and an error signal E.sub.1 is output from the comparator 106.
If a relation N.sub.1 &lt;N.sub.2 is satisfied in the comparator 107, this means that the frequency f.sub.4 of the CK.sub.4 is lower than its original frequency or the frequency f.sub.3 of the CK.sub.3 is higher than its original frequency, and an error signals E.sub.2 are output from the comparator 107.
The error signals E.sub.1 and E.sub.2 respectively output from the comparators 106 and 107 are input into a judging device 108 together with a timing pulse TP output from the timing generator 102, and an error flag EF indicative of abnormal clock CK.sub.1 or CK.sub.2 is output from the judging device 108.
As explained above, according to the conventional abnormal clock detecting apparatus, frequencies of two different clocks to be detected are divided, the rising and falling edges of the clocks divided by the two counters are counted, the counted results are added by the adder, the addition result and the reference value are compared with each other by the comparator, thereby detecting the abnormal clock.
In the conventional abnormal clock detector, however, the adder, comparator for calculating the counted values by the counter, and the timing generator for generating the reset pulse and timing pulse are required, which complicates the circuit structure of the detector.
Especially in the case of the abnormal clock detector disclosed in Japanese Patent Application Laid-open No. 4-306930, it is not possible to specify one of two clocks to be detected, and this circuit structure can not detect abnormal condition of three or more clocks.
Therefore, it is an object of the present invention to provide an abnormal clock detector and an abnormal clock detecting apparatus capable of detecting abnormal condition of three or more different clocks with a simple circuit structure.